The invention relates to a fading circuit for video signals comprising samples encoded as a k bit binary code, where k is an integer greater than 1. The fading circuit comprises n video signal inputs, where n is an integer, each video signal input being connected to a first set of inputs of a respective digital multiplier, n fading control signal inputs for fading control signals in the form of m bit binary signals, where m is an integer greater than 1, each fading control signal input being connected to a second set of inputs of the respective digital multipliers, each digital multiplier having an (k+m) bit output, at least the (k+1) most significant bits of which outputs are connected to respective inputs of an adding arrangement, and means for connecting the k most significant bits of the adding arrangement output to the output of the fading circuit as the output video signal.
Video signal manipulation in television studio equipment is increasingly being carried out on video signals which have been converted into digital form. The video signal is generally converted into an eight bit PCM encoded signal at a sampling rate of 13.5 Mhz. A fading circuit for a digitally encoded video signal normally comprises a digital multiplier having a first set of inputs to which the digital video signal is applied and a second set of inputs to which a fading control signal is applied. The fading control signal will also normally be an eight bit binary signal. As a result the multiplier will produce a sixteen bit output. This sixteen bit output has to be truncated to eight bits in order that the video signal can be transmitted to the rest of the system. It has been discovered however that a simple truncation of the sixteen bit output of the multiplier to eight bits gives disturbing results on display at certain settings of the fader control signal. Thus although the truncation gives mathematically correct results the eventual picture displayed contains disturbing amplitude variations.